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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">TRCCONFIGR, Trace Configuration Register</h1><p>The TRCCONFIGR characteristics are:</p><h2>Purpose</h2>
        <p>Controls the tracing options.</p>
      <h2>Configuration</h2><p>AArch64 System register TRCCONFIGR bits [31:0] are architecturally mapped to External register <a href="ext-trcconfigr.html">TRCCONFIGR[31:0]</a>.</p><p>This register is present only when FEAT_ETE is implemented and FEAT_TRC_SR is implemented. Otherwise, direct accesses to TRCCONFIGR are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>TRCCONFIGR is a 64-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_19">RES0</a></td></tr><tr class="firstrow"><td class="lr" colspan="13"><a href="#fieldset_0-63_19">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-18_18-1">ITO</a></td><td class="lr" colspan="2"><a href="#fieldset_0-17_16">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_15-1">VMIDOPT</a></td><td class="lr" colspan="2"><a href="#fieldset_0-14_13-1">QE</a></td><td class="lr" colspan="1"><a href="#fieldset_0-12_12-1">RS</a></td><td class="lr" colspan="1"><a href="#fieldset_0-11_11-1">TS</a></td><td class="lr" colspan="3"><a href="#fieldset_0-10_8">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-7_7-1">VMID</a></td><td class="lr" colspan="1"><a href="#fieldset_0-6_6-1">CID</a></td><td class="lr" colspan="1"><a href="#fieldset_0-5_5">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-4_4-1">CCI</a></td><td class="lr" colspan="1"><a href="#fieldset_0-3_3-1">BB</a></td><td class="lr" colspan="2"><a href="#fieldset_0-2_1">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0">RES1</a></td></tr></tbody></table><h4 id="fieldset_0-63_19">Bits [63:19]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-18_18-1">ITO, bit [18]<span class="condition"><br/>When TRCIDR0.ITE == 1:
                        </span></h4><div class="field">
      <p>Instrumentation Trace Override.</p>
    <table class="valuetable"><tr><th>ITO</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Instrumentation Trace Override disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Instrumentation Trace Override enabled.</p>
        </td></tr></table>
      <p>This field is ignored when <span class="function">SelfHostedTraceEnabled</span>() returns TRUE.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Trace unit reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-18_18-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-17_16">Bits [17:16]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-15_15-1">VMIDOPT, bit [15]<span class="condition"><br/>When TRCIDR2.VMIDOPT == 0b01:
                        </span></h4><div class="field">
      <p>Virtual context identifier selection control.</p>
    <table class="valuetable"><tr><th>VMIDOPT</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p><a href="AArch64-vttbr_el2.html">VTTBR_EL2</a>.VMID is used as the Virtual context identifier.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p><a href="AArch64-contextidr_el2.html">CONTEXTIDR_EL2</a>.PROCID is used as the Virtual context identifier.</p>
        </td></tr></table></div><h4 id="fieldset_0-15_15-2"><span class="condition"><br/>When TRCIDR2.VMIDOPT == 0b00:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    <p>Virtual context identifier selection control.</p>
<p><a href="AArch64-vttbr_el2.html">VTTBR_EL2</a>.VMID is used as the Virtual context identifier.</p></div><h4 id="fieldset_0-15_15-3"><span class="condition"><br/>When TRCIDR2.VMIDOPT == 0b10:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    <p>Virtual context identifier selection control.</p>
<p><a href="AArch64-contextidr_el2.html">CONTEXTIDR_EL2</a>.PROCID is used as the Virtual context identifier.</p></div><h4 id="fieldset_0-15_15-4"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-14_13-1">QE, bits [14:13]<span class="condition"><br/>When TRCIDR0.QSUPP == 0b01:
                        </span></h4><div class="field">
      <p>Q element generation control.</p>
    <table class="valuetable"><tr><th>QE</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>Q elements are disabled.</p>
        </td></tr><tr><td class="bitfield">0b01</td><td><p>Q elements with instruction counts are enabled.</p>
<p>Q elements without instruction counts are disabled.</p></td></tr></table>
      <p>All other values are reserved.</p>
    </div><h4 id="fieldset_0-14_13-2"><span class="condition"><br/>When TRCIDR0.QSUPP == 0b10:
                        </span></h4><div class="field">
      <p>Q element generation control.</p>
    <table class="valuetable"><tr><th>QE</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>Q elements are disabled.</p>
        </td></tr><tr><td class="bitfield">0b11</td><td><p>Q elements with instruction counts are enabled.</p>
<p>Q elements without instruction counts are enabled.</p></td></tr></table>
      <p>All other values are reserved.</p>
    </div><h4 id="fieldset_0-14_13-3"><span class="condition"><br/>When TRCIDR0.QSUPP == 0b11:
                        </span></h4><div class="field">
      <p>Q element generation control.</p>
    <table class="valuetable"><tr><th>QE</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>Q elements are disabled.</p>
        </td></tr><tr><td class="bitfield">0b01</td><td><p>Q elements with instruction counts are enabled.</p>
<p>Q elements without instruction counts are disabled.</p></td></tr><tr><td class="bitfield">0b11</td><td><p>Q elements with instruction counts are enabled.</p>
<p>Q elements without instruction counts are enabled.</p></td></tr></table>
      <p>All other values are reserved.</p>
    </div><h4 id="fieldset_0-14_13-4"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-12_12-1">RS, bit [12]<span class="condition"><br/>When TRCIDR0.RETSTACK == 1:
                        </span></h4><div class="field">
      <p>Return stack control.</p>
    <table class="valuetable"><tr><th>RS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Return stack is disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Return stack is enabled.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Trace unit reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-12_12-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-11_11-1">TS, bit [11]<span class="condition"><br/>When TRCIDR0.TSSIZE != 0b00000:
                        </span></h4><div class="field">
      <p>Global timestamp tracing control.</p>
    <table class="valuetable"><tr><th>TS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Global timestamp tracing is disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Global timestamp tracing is enabled.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Trace unit reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-11_11-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-10_8">Bits [10:8]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-7_7-1">VMID, bit [7]<span class="condition"><br/>When TRCIDR2.VMIDSIZE != 0b00000:
                        </span></h4><div class="field">
      <p>Virtual context identifier tracing control.</p>
    <table class="valuetable"><tr><th>VMID</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Virtual context identifier tracing is disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Virtual context identifier tracing is enabled.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Trace unit reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-7_7-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-6_6-1">CID, bit [6]<span class="condition"><br/>When TRCIDR2.CIDSIZE != 0b00000:
                        </span></h4><div class="field">
      <p>Context identifier tracing control.</p>
    <table class="valuetable"><tr><th>CID</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Context identifier tracing is disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Context identifier tracing is enabled.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Trace unit reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-6_6-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-5_5">Bit [5]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-4_4-1">CCI, bit [4]<span class="condition"><br/>When TRCIDR0.TRCCCI == 1:
                        </span></h4><div class="field">
      <p>Cycle counting instruction tracing control.</p>
    <table class="valuetable"><tr><th>CCI</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Cycle counting instruction tracing is disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Cycle counting instruction tracing is enabled.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Trace unit reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-4_4-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-3_3-1">BB, bit [3]<span class="condition"><br/>When TRCIDR0.TRCBB == 1:
                        </span></h4><div class="field">
      <p>Branch broadcasting control.</p>
    <table class="valuetable"><tr><th>BB</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Branch broadcasting is disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Branch broadcasting is enabled.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Trace unit reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-3_3-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-2_1">Bits [2:1]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-0_0">Bit [0]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES1</span>.</p>
    </div><div class="access_mechanisms"><h2>Accessing TRCCONFIGR</h2>
        <p>Must always be programmed.</p>

      
        <p>TRCCONFIGR.QE must be set to <span class="binarynumber">0b00</span> if TRCCONFIGR.BB is not 0.</p>

      
        <p>Writes are <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span> if the trace unit is not in the Idle state.</p>
      <p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRS &lt;Xt&gt;, TRCCONFIGR</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b10</td><td>0b001</td><td>0b0000</td><td>0b0100</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; CPTR_EL3.TTA == '1' then
        UNDEFINED;
    elsif CPACR_EL1.TTA == '1' then
        AArch64.SystemAccessTrap(EL1, 0x18);
    elsif EL2Enabled() &amp;&amp; CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT) &amp;&amp; (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') &amp;&amp; HDFGRTR_EL2.TRC == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; CPTR_EL3.TTA == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif IsFeatureImplemented(FEAT_TRBE_EXT) &amp;&amp; OSLSR_EL1.OSLK == '0' &amp;&amp; HaltingAllowed() &amp;&amp; EDSCR2.TTA == '1' then
        Halt(DebugHalt_SoftwareAccess);
    else
        X[t, 64] = TRCCONFIGR;
elsif PSTATE.EL == EL2 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; CPTR_EL3.TTA == '1' then
        UNDEFINED;
    elsif CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; CPTR_EL3.TTA == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif !ELUsingAArch32(EL1) &amp;&amp; IsFeatureImplemented(FEAT_TRBE_EXT) &amp;&amp; OSLSR_EL1.OSLK == '0' &amp;&amp; HaltingAllowed() &amp;&amp; EDSCR2.TTA == '1' then
        Halt(DebugHalt_SoftwareAccess);
    else
        X[t, 64] = TRCCONFIGR;
elsif PSTATE.EL == EL3 then
    if CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif !ELUsingAArch32(EL1) &amp;&amp; IsFeatureImplemented(FEAT_TRBE_EXT) &amp;&amp; OSLSR_EL1.OSLK == '0' &amp;&amp; HaltingAllowed() &amp;&amp; EDSCR2.TTA == '1' then
        Halt(DebugHalt_SoftwareAccess);
    else
        X[t, 64] = TRCCONFIGR;
                </p><h4 class="assembler">MSR TRCCONFIGR, &lt;Xt&gt;</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b10</td><td>0b001</td><td>0b0000</td><td>0b0100</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; CPTR_EL3.TTA == '1' then
        UNDEFINED;
    elsif CPACR_EL1.TTA == '1' then
        AArch64.SystemAccessTrap(EL1, 0x18);
    elsif EL2Enabled() &amp;&amp; CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT) &amp;&amp; (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') &amp;&amp; HDFGWTR_EL2.TRC == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; CPTR_EL3.TTA == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif IsFeatureImplemented(FEAT_TRBE_EXT) &amp;&amp; OSLSR_EL1.OSLK == '0' &amp;&amp; HaltingAllowed() &amp;&amp; EDSCR2.TTA == '1' then
        Halt(DebugHalt_SoftwareAccess);
    else
        TRCCONFIGR = X[t, 64];
elsif PSTATE.EL == EL2 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; CPTR_EL3.TTA == '1' then
        UNDEFINED;
    elsif CPTR_EL2.TTA == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; CPTR_EL3.TTA == '1' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif !ELUsingAArch32(EL1) &amp;&amp; IsFeatureImplemented(FEAT_TRBE_EXT) &amp;&amp; OSLSR_EL1.OSLK == '0' &amp;&amp; HaltingAllowed() &amp;&amp; EDSCR2.TTA == '1' then
        Halt(DebugHalt_SoftwareAccess);
    else
        TRCCONFIGR = X[t, 64];
elsif PSTATE.EL == EL3 then
    if CPTR_EL3.TTA == '1' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    elsif !ELUsingAArch32(EL1) &amp;&amp; IsFeatureImplemented(FEAT_TRBE_EXT) &amp;&amp; OSLSR_EL1.OSLK == '0' &amp;&amp; HaltingAllowed() &amp;&amp; EDSCR2.TTA == '1' then
        Halt(DebugHalt_SoftwareAccess);
    else
        TRCCONFIGR = X[t, 64];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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